1. Field of the Invention
This invention generally relates to an address generator for generating addresses, at which data to be accessed is stored, assigned to locations of a memory provided in a digital signal processor (hereunder abbreviated as a DSP) and of an external storage, and more particularly to a multidimensional address generator for generating addresses assigned to locations of a memory, in which data (e.g., image data) to be accessed is physically arranged as a one-dimensional array is stored, when accessing and treating the data as a multidimensional array (i.e., an array of two or more dimensions).
2. Description of the Related Art
Generally, when two-dimensional data such as image data is stored in a memory, it is required to perform a mapping of the two-dimensional data into a one-dimensional address space. In case of image data, a mapping of image data to one-dimensional addresses is usually carried out in accordance with order of raster scan of positions corresponding to the image data. Further, when the image data is treated as two-dimensional data, it is often to extract a part of image data corresponding to picture elements (i.e., pixels) of a rectangular region from all of the image data and use the extracted part of the image data for various image processing. In case of image data which is a typical example of two-dimensional data, such rectangular regions including, for instance, 3.times.3 or 8.times.8 pixels are employed as processing objects of various picture processing to be performed by using image data corresponding to pixels of a local neighborhood of a pixel and as objects of image data compression to be effected by dividing an entire image into image blocks.
Referring to FIGS. 4(a), (b) and (c), there is illustrated the manner of mapping image data into a one-dimensional address space. In these figures, reference numeral 41 indicates an entire image composed of a rectangular region including Q.sub.1 .times.Q.sub.2 pixels (incidentally, reference characters Q.sub.1 and Q.sub.2 denote positive integers); 42 a rectangular region including P.sub.1 .times.P.sub.2 pixels to be accessed (incidentally, reference characters P.sub.1 and P.sub.2 designate positive integers and P.sub.1 .ltoreq.Q.sub.1 and P.sub.2 .ltoreq.Q.sub.2); 43A an actual memory map corresponding to the entire image; and 43B another actual memory map corresponding to the rectangular region 42 to be accessed.
As illustrated in FIGS. 4(a), (b) and (c), the rectangular region 42 arbitrarily extracted from the entire image comprised of the rectangular region including Q.sub.1 .times.Q.sub.2 pixels is divided and arrayed in a memory. Thus, in order to successively access image data included in the rectangular region 42 to be accessed, and address generator for generating addresses is needed. Further, a direct memory access (DMA) transfer of image data from an external image memory to an internal image memory of a DSP is performed by using this address generator, and then the DSP effects various processing of the transferred image data in synchronization with the access by the address generator to the image memories.
Referring next to FIG. 10, there is shown an example of a conventional two-dimensional address generator. Here, as illustrated in FIG. 4, a rectangular region including P.sub.1 .times.P.sub.2 pixels in an entire image comprised of a rectangular region including Q.sub.1 .times.Q.sub.2 is employed as an object to be accessed.
In FIG. 10, reference numeral 101 denotes a first increment setting device for setting an increment to be used to calculate addresses assigned to locations at which image data corresponding to pixels arranged in a first scanning direction (i.e., a secondary scanning direction (e.g., X-direction as viewed in FIG. 4(a))) to be accessed is stored; 102 and adder; 103 an accumulating register; 104 a start-address setting device for setting and address (hereunder referred to simply as a start address) from which an operation of accessing image data is started; and 105 a control circuit. Incidentally, in the instant specification, a direction, in which elements such as pixels to be accessed are arranged, will be referred to as a scanning direction.
Hereinafter, an operation of this conventional two-dimensional address generator will be described with reference to FIG. 10.
First, in Cycle 0, data (hereunder referred to as start-address data) indicating an address, which corresponds to image data 0 of a pixel to first be accessed in the rectangular region 42 of FIG. 4(a), of the map 43A of FIG. 4(b) is set by the start-address setting device 104 in the accumulating register 103 as an initial value of an address (i.e., a start address) corresponding to image data of a pixel to be accessed.
Thereafter, in Cycles P.sub.1, 2P.sub.1, . . . and (P.sub.2 -1)P.sub.1, the start-address setting device sets addresses of locations, at which image data P.sub.1, 2P.sub.1, . . . and (P.sub.2 -1)P.sub.1 are stored, of an image memory, in the accumulating register 103, respectively, as a start address. Further, in each of Cycles 1, . . . and (P.sub.1 -1), data held in the accumulating register 103 is added to the first increment set by the first increment data setting device 101 by the adder 102, and moreover a result of the addition is written to the accumulating register 103. Similarly, an addition of data held in the accumulating register 103 to the first increment, as well as a writing of a result of the addition to the accumulating register 103, is performed in each of Cycles (P.sub.1 +1) to (2P.sub.1 -1) and (P.sub.2 -n 1)P.sub.1 to (P.sub.2 P.sub.1 -1). Finally, the conventional two-dimensional address generator outputs data obtained in the accumulating register 103 as a result of performing operations of Cycles 0 to (P.sub.2 P.sub.1 -1).
With the configuration of FIG. 10, the conventional address generator, however, needs to calculate a start address and set the calculated start address in the accumulating register 103 every time the scanning direction is changed. Thus, the conventional address generator has a drawback in that many number of cycles are needed to generate addresses required to access multidimensional data such as image data. The present invention is created to eliminate the above described drawback of the conventional address generator.
Accordingly, and object of the present invention is to provide a multidimensional address generator which can access multidimensional data by performing a relatively small number of cycles.
Further, another object of the present invention is to provide a control system for controlling a multidimensional address generator such that the address generator can have successive accesses to a specific address of a memory (for example, can read data stored at a specific address of a memory, then perform an operation on the read data and further write a result of the operation to the specific address of the memory).